module mips_Hmini(clk,rst_all);
  	input clk,rst_all;
  	wire [1:0]ExtOp,ALUctr,nPC_sel; 
  	wire ALUSrc,MemWr,MemtoReg,RegDst,RegWr,j_sel,rst_all;
  	wire [31:0]instruction;
  

	//module ctrl(instruction,RegDst,RegWr,ExtOp,nPC_sel,ALUctr,MemtoReg,MemWr,ALUSrc,j_sel,rst_all);
  	//all  control signal
	ctrl CU(.instruction(instruction),  
		.RegDst(RegDst),
		.RegWr(RegWr),.ExtOp(ExtOp),
		.nPC_sel(nPC_sel),.ALUctr(ALUctr),
		.MemtoReg(MemtoReg),
		.MemWr(MemWr),
		.ALUSrc(ALUSrc),
		.j_sel(j_sel),
		.rst(rst_all)
		);

	//all components in datapath
  	mips_datapath MAIN(
		.clk(clk),
		.rst(rst_all),
		.RegDst(RegDst),
		.RegWr(RegWr),
		.ExtOp(ExtOp),
		.nPC_sel(nPC_sel),
		.ALUctr(ALUctr),
		.MemtoReg(MemtoReg),
		.MemWr(MemWr),
		.ALUSrc(ALUSrc),
		.j_sel(j_sel),
		.Instruction(instruction)
		);

endmodule
  

